1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a single damascene process or a dual damascene process is adopted.
2. Description of the Related Art
A copper (Cu) wiring gives a semiconductor device a lower resistance, a smaller capacity and higher reliability than an aluminum (Al) alloy wiring line gives. Thus, the importance of the copper wiring has increased in a micro-element in which circuit delay due to a parasitic resistance and a parasitic capacity of a wiring are dominant. In general, since unlike the Al alloy wiring, it is not easy to etch away Cu by utilizing a dry etching method, a single damascene process is generally accepted for Cu. The single damascene process is a process for a wiring. In this process, a predetermined trench is previously formed in an interlayer insulating film formed of, for example, a silicon oxide (SiO2) film, a wiring material is filled in the predetermined trench, and thereafter the excessive wiring material is removed by utilizing a chemical mechanical polishing (CMP) method or the like, thereby forming the desired wiring. Moreover, a dual damascene method in which after a contact hole and a wiring trench are formed, a wiring material is collectively filled in the contact hole and the wiring trench, and the excessive wiring material is then removed is also effective in reduction in the number of processes and the cost. This technique, for example, is disclosed in Japanese Patent Laid-open No. Hei 11-45887.
As a design rule for LSI has proceeded to scale down, a rate containing a barrier metal used to prevent scattering in a surface of a Cu wiring and grain boundaries or diffusion of Cu into an insulating film has increased. As a result, it is a problem that an abrupt increase in wiring resistance is generated due to an influence of such an increase or the like, which causes reduction in a processing speed of a semiconductor device. Moreover, the barrier metal is deposited in overhang-like shape in an upper end of the trench or the contact hole by utilizing a PVD method. As a result, there is also encountered such a problem that as the LSI design rule has proceeded to scale down, it is easy to generate a void when a wiring material (Cu in a normal case) is deposited.
As for the means for solving the above-mentioned problems, a method of thinning a barrier metal, or a method of forming a barrierless structure without using any of the barrier metals is well known. With regard to the thinning of the barrier metal, there is known a method of simply thinning the barrier metal deposited by utilizing the PVD method which is generally used. In addition thereto, recently, the barrier metal which is deposited by utilizing an atomic layer deposition (ALD) method has come to attract attention. In addition, with regard to the barrierless structure, in addition to a method of using a film which has a low diffusion coefficient of Cu and which is made of, for example, benzocychrobutene (BCB) as an insulating film, a method is known in which Cu is mixed with a metal such as magnesium (Mg) or aluminum (Al), whereby the barrier property is enhanced while an increase in wiring resistance is suppressed. This method is disclosed for example in T. Usui et al., “Low Resistive and Highly Reliable Cu Dual-Damascene Interconnect Technology Using Self-Formed MnSixOy Barrier Layer”, Proceeding of IEEE IITC, 2005.
The barrierless structure or the thinning of the barrier metal makes it possible to reduce the wiring resistance of the semiconductor device. However, the following problems are caused in the CMP process when the wiring is formed. Hereinafter, these problems will be described by giving the barrierless structure as an example.
FIG. 4A is a process cross sectional view before the CMP is performed in the single damascene process or the dual damascene process. As shown in FIG. 4A, a wiring trench is formed in an interlayer insulating film 102 on a base substrate 101, and a conductive layer 104 made of Cu or the like is formed over the interlayer insulating film 102 so as to fill in the wiring trench. Normally, a swelling amount of conductive layer 104 in a region having a high wiring density becomes high, while a swelling amount of conductive layer 104 in a region having a low wiring density becomes low.
After that, the conductive layer 104 is subjected to the CMP in order to remove the excessive conductive layer 104 on the interlayer insulating film 102. The CMP includes a first step of flattening the conductive layer 104 by removing the excessive conductive layer 104 made of Cu, and a second step of removing surfaces of the conductive layer 104 and the interlayer insulating film 102 while the flattening of the conductive layer 104 is maintained. In the second step, in general, in order to remove a facet of the wiring which is generated during the processing, a slurry for substantially equalizing the polishing rates of the conductive layer 104 and the interlayer insulating film 102 to each other is used, and the polishing is performed until a desired wiring height is obtained while the flattening is maintained.